Ferroelectric metal oxide ceramic materials such as lead zirconate titanate (PZT) have been investigated for use in ferroelectric semiconductor memory devices. Other ferroelectric materials, for example, strontium bismuth tantalate (SBT) can also be used. FIG. 1 shows a conventional ferroelectric memory cell 105 having a transistor 130 and a ferroelectric capacitor 140. A capacitor electrode 142 is coupled to a plateline 170 and another capacitor electrode 141 is coupled to the transistor which selectively couples or decouples the capacitor from a bitline 160, depending on the state (active or inactive) of a wordline 150 coupled to the transistor gate.
The ferroelectric memory stores information in the capacitor as remanent polarization. The logic value stored in the memory cell depends on the polarization of the ferroelectric capacitor. To change the polarization of the capacitor, a voltage which is greater than the switching voltage (coercive voltage) needs to be applied across its electrodes. An advantage of the ferroelectric capacitor is that it retains its polarization state after power is removed, resulting in a non-volatile memory cell.
FIG. 2 shows a plurality of ferroelectric memory cells configured in a chain 202. Such a memory architecture is described in, for example, Takashima et al., 1997 Symposium on VLSI Circuits Digest of Technical Papers, p.83f and Takashima et al., IEEE J. Solid-State Circuits, vol. 33, pp 787-792, May 1998, which are herein incorporated by reference for all purposes. The memory cells 205 of the chain, each with a transistor 230 coupled to a capacitor 240 in parallel, are coupled in series. The gates of the cell transistors are, for example, gate conductors which either serve as or are coupled to wordlines. One end 213 of the chain is coupled to a bitline while the other end 214 is coupled to a plateline. A plurality of chains are interconnected or addressed by wordlines to form a memory block or array.
FIG. 3 shows a conventional cross-section of a memory chain 302. As shown, the transistors 330 of the memory cells are formed on a substrate 310. Adjacent cell transistors share a common diffusion region. The capacitors 340 of the memory chain are grouped in pairs. The bottom electrode 341 serves as a common electrode for adjacent capacitors. The top electrode 342 of a capacitor from a capacitor pair is coupled to the top electrode of a capacitor of an adjacent pair, thus forming a daisy chain. The top capacitor electrodes are coupled to the cell transistors via active area top electrode (AATE) plugs 386.
Conventionally, coupling of the top electrodes of adjacent capacitor pairs is achieved with plugs 348 and a conductive line 362. As a result, the use of chained architectures requires an additional metal process, which includes formation of contact plugs and metal lines. The need for additional metal process increases manufacturing costs as well as raw process time. Furthermore, the formation of contacts requires an additional patterning or etching step which creates additional etch damage.
FIG. 4 shows a top view of two adjacent capacitor pairs 309 of a memory chain. An upper capacitor electrode plug 386 is located between the capacitor pairs. The use of such upper capacitor electrode plugs requires a spacing of 3F between the capacitor pairs, where F is the feature size or ground rule of the IC. One F is required on each side of the plug for separation from the bottom electrodes of the adjacent capacitor pairs while one F is required for the plug. The needed spacing undesirably increases the cell size.
From the foregoing discussion, it is desirable to provide a chained architecture without needing an additional metal process as well as reducing cell size.